GPU ROADMAP 2026–2028
Release timeline for next-generation data center GPUs from NVIDIA, AMD, Google, and Intel. Updated as new information becomes available.
2026
8 GPUsNVIDIA B300 Ultra
NVIDIAAvailableProcess
TSMC 4NP
Memory
288GB HBM3e
FP8 TFLOPS
7,000
TDP
1,400W
Key Feature
2× H100 per GPU, 10 TB/s memory bandwidth
Blackwell Ultra generation. Shipping in limited quantity to hyperscalers and cloud providers.
AMD Instinct MI350X
AMDAvailableProcess
TSMC 3nm
Memory
288GB HBM3e
FP8 TFLOPS
4,600
TDP
1,000W
Key Feature
CDNA4 architecture, 8 TB/s memory bandwidth
AMD's CDNA4 generation. Competitive with B200 on VRAM; still ramps to availability.
NVIDIA B300A
NVIDIAAnnouncedProcess
TSMC 4NP
Memory
288GB HBM3e (unified CPU+GPU)
FP8 TFLOPS
TBD
TDP
~1,200W
Key Feature
ARM Neoverse CPU + Blackwell GPU die — full unified memory
Grace Blackwell Ultra variant. Targeting workloads that benefit from unified CPU-GPU memory addressing.
Google TPU v7 Ironwood
GOOGLEAvailableProcess
Custom ASIC
Memory
192GB HBM per chip
FP8 TFLOPS
4,600
TDP
~600W
Key Feature
GA April 2026 · 4× efficiency vs Trillium · pod scales to 9,216 chips (42.5 ExaFLOPS)
Generally available on GCP since April 22, 2026. Designed as Google's first TPU for the age of inference. SparseCores improve sparse-model throughput. Best for JAX-native workloads.
AMD Instinct MI355X
AMDAvailableProcess
TSMC 3nm
Memory
288GB HBM3e
FP8 TFLOPS
4,610
TDP
1,400W
Key Feature
Highest VRAM of any commercially available GPU
Premium CDNA4 variant. Maximum VRAM configuration for very large model training.
AMD Instinct MI400X
AMDAnnouncedProcess
TSMC 2nm
Memory
432GB HBM4 · 19.6 TB/s
FP8 TFLOPS
~20,000 (est.)
TDP
TBD
Key Feature
CDNA5 architecture · 40 PFLOPS FP4 · 12 chiplets · Helios rack with EPYC Venice CPUs
AMD confirmed MI400 series for 2026 on TSMC 2nm. 432GB HBM4 per GPU — 50% more than MI355X. Pairs with EPYC Venice CPUs and Pensando Vulcano NICs in Helios rack solution. Ships as MI455X / MI430X variants.
NVIDIA Vera Rubin (R200)
NVIDIAAnnouncedProcess
TSMC 3nm
Memory
288GB HBM4 per chip · 22 TB/s
FP8 TFLOPS
~12,500 (est.)
TDP
TBD
Key Feature
NVLink 6.0 (3.6 TB/s) · NVL144 rack = 3.6 ExaFLOPS FP4 · 2.8× Blackwell bandwidth
Announced at CES 2026. Dual-die chip on TSMC 3nm, 336B transistors. NVL144 rack pairs 144 Rubin GPUs with 36 Vera CPUs. Mass production targeted Q3/Q4 2026, broad cloud availability 2027.
Intel Jaguar Shores
INTELAnnouncedProcess
Intel 18A
Memory
HBM4 (est., SK Hynix)
FP8 TFLOPS
TBD
TDP
TBD
Key Feature
Unifies Gaudi ASIC + Xe-HPC GPU · silicon photonics interconnects · rack-scale disaggregated arch
Renamed from Falcon Shores. Design closure targeted H1 2026, volume production H2 2026. Uses Intel 18A process with silicon photonics for high-bandwidth interconnects. Succeeds Gaudi 3.
2027
3 GPUsGoogle TPU v8
GOOGLERumoredProcess
Custom ASIC
Memory
TBD
FP8 TFLOPS
TBD
TDP
TBD
Key Feature
Liquid cooling, 2× TPU v7 performance target
Expected to maintain Google's ~2-year generation cadence. Likely announced at Google Next 2027.
NVIDIA Rubin Ultra (RU100)
NVIDIARumoredProcess
TSMC 3nm
Memory
TBD (HBM4e)
FP8 TFLOPS
~14,000 (est.)
TDP
TBD
Key Feature
Rubin Ultra refresh — follows Blackwell → Blackwell Ultra pattern
Based on NVIDIA's Ultra refresh cadence (H100→H200, B200→B300). Expected 2–3 quarters after base Rubin.
AMD Instinct MI450X
AMDRumoredProcess
TSMC 2nm (est.)
Memory
TBD (HBM4e est.)
FP8 TFLOPS
TBD
TDP
TBD
Key Feature
CDNA6 architecture target
AMD's roadmap targets annual GPU architecture updates. MI450X expected to compete with Rubin Ultra.
Disclaimer
Specs for "Announced" and "Rumored" GPUs are estimates based on official announcements, roadmap slides, and reputable industry sources. Actual specs, pricing, and availability dates may differ significantly. GPUAdvisor updates this page as new information becomes available.
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